1. Field of the Invention
The present invention relates to an array substrate for a display device, and more particularly, to an array substrate for a display device that includes a thin film transistor having excellent properties and a method of fabricating the array substrate.
2. Discussion of the Related Art
As the society has entered in earnest upon an information age, a field of display devices that represent all sorts of electrical signals as visual images has developed rapidly. Particularly, the liquid crystal display (LCD) device or the OELD device as a flat panel display device having characteristics of light weight, thinness and low power consumption is developed to be used as a substitute for a display device of cathode-ray tube type.
Since the LCD device including a thin film transistor (TFT) as a switching element, referred to as an active matrix LCD (AM-LCD) device, has excellent characteristics of high resolution and displaying moving images, the AM-LCD device has been widely used.
On the other hand, since the OELD device has excellent characteristics of high brightness, a low power consumption and high contrast ratio, the OELD device has been widely used. Moreover, the OELD device has advantages of a high response rate, a low production cost and so on.
Both the LCD device and the OELD device require an array substrate including a thin film transistor (TFT) as a switching element for controlling on and off of each pixel region. In addition, the OELD device requires another TFT as a driving element for driving an organic electroluminescent diode in each pixel region.
FIG. 1 is a cross-sectional view of a portion of the related art array substrate for the display device. For convenience of explanation, a region, where a TFT is formed, is defined as a switching region TrA.
In FIG. 1, the array substrate includes a substrate 11 including a pixel region P and the switching region TrA. On the substrate 11, a gate line (not shown) and a data line 33 are formed to define the pixel region P. The gate line and the data line 33 cross each other to define the pixel region. In the switching region TrA in the pixel region P, a gate electrode 15 is formed, and a gate insulating layer 18 covers the gate electrode 15. A semiconductor layer 28 including an active layer 22 and an ohmic contact layer 26 is formed on the gate insulating layer 18 and in the driving region TrA. The active layer 22 is formed of intrinsic amorphous silicon, and the ohmic contact layer 26 is formed of impurity-doped amorphous silicon. A source electrode 36 and a drain electrode 38, which is spaced apart from the source electrode 36, are formed on the semiconductor layer 28. A portion of the ohmic contact layer 26 corresponding to a space between the source and drain electrodes 36 and 38 is removed such that a center of the active layer 22 is exposed through the space between the source and drain electrodes 36 and 38.
The gate electrode 15, the gate insulating layer 18, the semiconductor layer 28, the source electrode 36 and the drain electrode 38 constitute the TFT Tr. The TFT is connected to the gate line, the data line 33 and the TFT Tr.
A passivation layer 42 including a drain contact hole 45 is formed on the TFT Tr. The drain contact hole 45 exposes the drain electrode 38 of the TFT Tr. A pixel electrode 50 contacting the drain electrode 38 of the TFT Tr is formed on the passivation layer 42 and in each pixel region P. A semiconductor pattern 29 including a first pattern 27, which is formed of the same material and disposed on the same layer as the ohmic contact layer 26, and a second pattern 23, which is formed of the same material and disposed on the same layer as the active layer 22, is disposed under the data line 33.
The active layer 22 has a difference in a thickness. Namely, a center portion, which is exposed through the space between the source and drain electrodes 36 and 38, of the active layer 22 has a first thickness t1, and a side portion, on which the ohmic contact layer 26 is formed, of the active layer 22 has a second thickness t2 being different from the first thickness t1. (t1≠t2) The thickness difference in the active layer 22 is caused by a fabricating method. Properties of the TFT are degraded by the thickness difference in the active layer 22.
FIGS. 2A to 2E are cross-sectional views showing a process for forming the semiconductor layer, the source electrode and the drain electrode in the related art array substrate. For convenience of explanation, the gate electrode and the gate insulating layer are not shown.
In FIG. 2A, an intrinsic amorphous silicon layer 20, an impurity-doped amorphous silicon layer 24, and a metal layer 30 are sequentially formed on the substrate 11. A photoresist (PR) layer (not shown) is formed on the metal layer 30 by coating a PR material. The PR layer is exposed and developed to form first and second PR patterns 91 and 92. The first PR pattern 91 corresponds to a portion, where source and drain electrodes are formed, and has a third thickness. The second PR pattern 92 corresponds to a portion of a space between the source and drain electrodes, and has a fourth thickness smaller than the third thickness.
Next, in FIG. 2B, the metal layer 30 (of FIG. 2A) exposed by the first and second PR patterns 91 and 92, the impurity-doped amorphous silicon layer 24 (of FIG. 2A) and the intrinsic amorphous silicon layer 20 (of FIG. 2A) under the metal layer 30 are etched to form a metal pattern 31, an impurity-doped amorphous silicon pattern 25 under the metal pattern 31, and an intrinsic amorphous silicon pattern 22 under the impurity-doped amorphous silicon pattern 25.
Next, in FIG. 2C, the second PR pattern 92 (of FIG. 2B) is removed by an ashing process. At the same time, the third thickness of the first PR pattern 91 (of FIG. 2B) is reduced such that a third PR pattern 93 having a thickness smaller than the third thickness is formed on the metal pattern 31.
Next, in FIG. 2D, a center portion of the metal pattern 31 (of FIG. 2C) exposed by the third PR pattern 93 is etched to form the source electrode 36 and the drain electrode 38 spaced from the source electrode 36. By etching the metal pattern 31, a center portion of the impurity-doped amorphous silicon pattern 25 is exposed through the space between the source electrode 36 and the drain electrode 38.
Next, in FIG. 2E, the exposed center portion of the impurity-doped amorphous silicon pattern 25 (of FIG. 2D) is dry-etched to form the ohmic contact layer 26 under the source electrode 36 and the drain electrode 38. In this case, the dry-etching process for the exposed center portion of the impurity-doped amorphous silicon pattern is performed during a sufficient long time to completely remove the exposed center portion of the impurity-doped amorphous silicon pattern. By dry-etching the exposed center portion of the impurity-doped amorphous silicon pattern, a center portion of the active layer 22 of intrinsic amorphous silicon is partially etched. However, a side portion of the active layer 22 is not etched because the ohmic contact layer 26 blocks the side portion of the active layer 22. As a result, the active layer 22 has a thickness difference. (t1≠t2)
If the dry-etching process for the exposed center portion of the impurity-doped amorphous silicon pattern is not performed during a sufficient long time to avoid the thickness difference, the impurity-doped amorphous silicon may remain on the active layer 22 such that properties of the TFT is degraded. Accordingly, it is required to perform the dry-etching process for the exposed center portion of the impurity-doped amorphous silicon pattern during a sufficient long time.
Accordingly, in the above fabricating process for the related art array substrate, the thickness difference in the active layer is an inevitable result such that properties of the TFT is degraded.
In addition, since the intrinsic amorphous silicon layer for the active layer should be formed with a sufficient thickness, for example, more than about 1000 Å, considering etched thickness, production yield is reduced and production cost is increased.
Generally, the active layer for the TFT is formed of intrinsic amorphous silicon. Since atoms of intrinsic amorphous silicon are randomly arranged, it has a metastable state with light or an electric field such that there is a problem in stability as a TFT. In addition, since a carrier mobility in a channel is relatively low, i.e., 0.1 cm2/V·S˜1.01 cm2/V·S, there is a limitation in use of a driving element.
To resolve these problems, a fabricating method of a thin film transistor, which includes an active layer of polycrystalline silicon by crystallizing amorphous silicon into polycrystalline silicon through a crystallizing process with a laser beam apparatus, is introduced.
However, referring to FIG. 3, which shows a cross-sectional view of the related art array substrate including the active layer of polycrystalline silicon, a doping process is required. Namely, in the array substrate 51 including the TFT Tr, high concentration impurities should be doped into both sides of the center region 55a of the semiconductor layer 55 of polycrystalline silicon to form n+ region 55b. The region 55b may be p+ region depending on a kind of the impurities. Accordingly, an implantation apparatus for the doping process is required, so new process line is required and production costs are increased.